SRAM is conventionally used in applications where speed and low power are considerations. SRAM cells are fast and do not need to be dynamically updated, as in the case of Dynamic Random Access Memory (DRAM) cells. The structure of a conventional SRAM cell comprises two cross-coupled inverters, conventionally formed from four Complementary Metal Oxide Semiconductor (CMOS) transistors. The cross-coupled inverters form the basic storage element, with two stable states which represent the complementary binary values “0” and “1”. Two additional transistors, called “access transistors”, serve to control access to the storage element during read and write operations. Accordingly, a conventional SRAM cell architecture involves six transistors, and is generally referred to as a 6T SRAM cell.
FIG. 1 illustrates a conventional 6T SRAM cell 100. The storage element comprises transistors M1-M4. A write operation on cell 100 is initiating by driving word line WL to positive power supply voltage VDD. Access transistors M5 and M6 write the values on complementary bit lines into the storage element. In a read operation, the complementary bit lines are both pre-charged to a predefined value, which is conventionally VDD. Once the word line is activated, the complementary values stored in the storage element act to discharge one of the bit lines, while the other is maintained at the precharge voltage. Sense amplifiers (not shown) quickly drive the values on the discharged bit line to ground voltage VSS and the complementary bit line to VDD accordingly.
Due to process variation, the threshold voltage on access transistors M5 and M6 may be mismatched, which may lead to the value on one of the complementary nodes of the storage element not being transferred correctly to one of the complementary bit lines. In this scenario, it is possible that the value so withheld from being transferred, may drive the cross-coupled inverters to change their states to a spurious value. This problem is commonly referred to as read instability.
Similarly it is possible that a high threshold voltage on the access transistors may make it difficult to drive the values on the bit lines onto the storage element in a write operation. The writability of the SRAM cell is said to be low in such cases. It will be recognized that these and other problems are associated with conventional 6T SRAM architectures.
5T SRAM architectures have been explored in the past, in order to overcome some of the drawbacks associated with 6T SRAM structures. In general, 5T SRAM cells comprise a single bit line and an access transistor as opposed to the complementary bit line pair and two access transistors featured in 6T SRAM cells. For example, 5T SRAM structures have been presented in Hiep Tran, “Demonstration of 5T SRAM and 6T dual-port RAM cell arrays”, IEEE symposium on VLSI circuits digest, 1996, pp. 68-69, (hereinafter, “Tran”), which is incorporated in its entirety herein.
FIG. 2 illustrates a memory array according to Tran, comprising 5T SRAM cells. With reference to FIG. 2, a read operation is initiated by driving one of the word lines WL0-WLn high (i.e., positive power supply voltage, VDD). Write enable WE is driven low (i.e., ground, VSS), which in turn drives WEX high, turning transistor MnS on. This causes the source terminal of transistor M1 to be driven low, via pass transistor MnS. During a write operation, again, one of the word lines is high. In this case, write enable WE is high, and WEX is low, causing MnS to be turned off, and the source terminal of transistor M1 to be connected to capacitor Csrc.
Based on the foregoing discussion, it will be appreciated that the SRAM circuit of Tran suffers from additional transistors (for example, MnS and the inverter for generating signal WEX), and capacitors (Csrc) per column of the SRAM array. Since Csrc is connected to transistor M1 of all cells in the same column, the writability and stability of the storage element of the 5T SRAM are sensitive to the capacitance of Csrc. Further, this additional capacitance causes degradation of write time to the cells, rendering the 5T SRAM circuit of Tran slower than conventional 6T SRAM structures.
Another reference directed to 5T SRAM structures is Ingvar Carlson et al., “A high density, low leakage, 5T SRAM for embedded caches” IEEE ESSCIRC, September 2004, pp. 215-218 (hereinafter, “Carlson”), which is incorporated by reference in its entirety, herein. FIG. 3 illustrates the 5T SRAM structure proposed by Carlson in 180 nm technology. Carlson attempts to overcome problems of writeability and read instability by precharging bit line BL to a precharge voltage Vpc, wherein the value of Vpc lies between the positive supply voltage and ground, VDD and VSS.
During a read operation, the cell voltage Vcell, and the word line voltage VWL are driven to VDD, and the bit line is maintained at Vpc. The value of Vpc is such that, the bit line voltage is low enough not to cause contentions and spurious writes with the values stored in the storage element of the SRAM. A write operation of “0” into the storage element is achieved by driving the bit line voltage to VSS (while driving VWL and Vcell to VDD, as in the case of a read operation). The strength of access transistor M5 is configured such that the value of “0” (corresponding to voltage VSS at the bit line) can be easily driven into the storage element.
However, a write operation of “1” needs special consideration in Carlson. While Vcell and the word line voltage are at VDD, the bit line voltage is driven to VDD. In this case, the voltage that appears at node Q, as shown in FIG. 3 is VDD−Vth5, where Vth5 is the threshold voltage of access transistor M5. In order for a write operation of “1” to be successful, node Q is required to be driven all the way to VDD, in spite of the reduced voltage value of VDD−Vth5 which appears at the node. The transistors M1-M4 are resized as shown in FIG. 3, in order to overcome contention with the values stored in the cross-coupled inverters, and accomplish a write operation of “1”. Unfortunately, such unbalanced sizing of the transistors is detrimental to ease of layout, and results in an increased layout size of the SRAM bitcell. In fact, the 5T SRAM of Carlson may result in a layout size that is larger than conventional 6T SRAM circuits because additional circuitry is required to generate Vpc that is lower than VDD to avoid an invalid write of “1” during read operations. Further, as process variation increases with technology scaling, the 5T SRAM of Carlson is rendered highly unstable, because asymmetric and unbalanced inverters are highly vulnerable to threshold voltage mismatch in the respective transistors of the cross-coupled inverter.
Another drawback of Carlson is seen in the case of half selected cells. Half selected cells are SRAM cells, whose word line is selected, but bit line is unselected (bit line voltage is a floating VDD value). Conventionally, SRAM cells in columns of the memory array that do not contain a selected SRAM cell, are half selected. In half selected cells, if the transistor strength of access transistor M5 is high enough, a write of “1” may be forced into the storage element. The unbalanced transistor sizes of Carlson make the SRAM circuitry more susceptible to such invalid write operations.
As described previously, one of the expected benefits of 5T SRAMs over 6T SRAMs is a smaller layout size. However, due to additional capacitors and unbalanced transistor sizes, this benefit is not realized in Tran and Carlson. Moreover, these schemes suffer from read instability and low writeability. Accordingly there is a need in the art for 5T SRAM circuits with lower layout size than conventional 6T SRAM circuits and also improved read stability and writeability.